Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices. Most electronic devices are designed with a single flash memory device.
One type of synchronous flash memory device is a flash memory device that has a synchronous dynamic random access memory (SDRAM) interface. This enables the synchronous flash device to operate at much higher speeds than a typical flash memory. One type of synchronous flash memory device does not read one bit at a time, as in typical flash memories. These synchronous flash memories read an entire row of memory at once. In general, a synchronous flash memory allows reading and writing data in synchronization with an external clock.
FIG. 1 illustrates a diagram of a typical prior art row of a synchronous flash memory array. The row is comprised of number of cells 110-113 that store the charge. Typically, each row is made up of 4000 cells with 16 cells between array grounds. Each cell 110-113 is comprised of a drain connection 103 that is coupled to a bit line and a source connection 105 that is coupled to the memory array ground through a source line. A gate connection 107 is coupled to a word line, such as WL0, that controls access to that particular row of cells.
Each of the cells 110-113 has a drain-to-source resistance that is inherent in the cell's composition. This resistance may be in the 2 k to 10 k Ohm range depending on the topology of the cell. When one cell is read, the other cells in the row are also activated by the word line. Current flowing through the other cells in the row goes through the same path to array ground, effectively creating a number of parallel resistances on either side of the desired cell, if the cell is towards the middle of the row. The cell's effective source resistance varies depending on the location of the cell relative to the array ground.
When the cell is verified, the same resistance is present. Therefore, a cell that is furthest from the array ground tends to be erased further since there is a higher potential on its source as the cell current causes the local source voltage to rise. This voltage increase causes the cell Vgs and current to decrease.
A specific current level is expected for cell verification. Since the current is reduced, more erase pulses are sent in order to get the same current level as the cells that are closer to array ground. Therefore, the relative V1 of the cells after an erase operation, relative to their location to array ground, will be different. The cells furthest from array ground will have higher V1 levels than the cells closer to array ground.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative flash memories with improved erase verification levels.